The present invention relates generally to semiconductor processing and, more particularly, to semiconductor device formation having junction isolation.
In the manufacture of semiconductor devices such as MOSFETS, advances in process technology and digital system architecture have led to integrated circuits having increased operating frequencies. Unfortunately, higher operating frequencies result in undesirable increases in power consumption. Power consumption is a significant problem in integrated circuit design generally, and particularly in large scale, high speed products such as processors and microprocessors. Nonetheless, the trend of integrating more functions on a single substrate while operating at ever higher frequencies goes on unabated. One way to improve integrated circuit performance is by reducing the loading capacitance of metal-oxide-semiconductor field effect transistors (MOSFETs). Transistor loading capacitance generally has three components: intrinsic gate capacitance, overlap capacitance, and junction capacitance.
Junction capacitance occurs as a result of the capacitive coupling between the source and drain terminals of an FET with the underlying substrate, by virtue of the junction therebetween. One way to reduce junction capacitance is to form MOSFETs upon an insulating substrate. This is often referred to as silicon-on-insulator (SOI) technology. In a typical SOI process, junction capacitance is reduced through isolating junctions from the substrate by interposing a thick buried oxide layer. However, short-channel MOSFETs (constructed with thick buried oxide layers which isolate their junctions from the substrate) tend to have poor punch-through characteristics, poor short-channel characteristics and other effects related to the floating body. In addition, SOI technology is more expensive to implement and generally does not permit contact to the underlying substrate for device control.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for forming a field effect transistor (FET). In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further having a mesa region formed therein. A gate is formed within the active semiconductor region, the gate abutting the mesa region along one side thereof. Then, a source region is defined within a first area of the semiconductor region, the first region being located over an insulating layer. A drain region is defined within a second area of the semiconductor region, the second area also being located over the insulating layer. The first and second areas of the semiconductor region are located on opposite sides of the mesa region, and the insulating layer isolates the source region and the drain region from the substrate.
In a preferred embodiment, the active semiconductor region is formed by forming the insulating layer upon the substrate. Then, a window opening is formed within the insulating layer and an epitaxial layer is grown over the insulating layer and the window opening, wherein the mesa region is formed over the window opening. Preferably, the insulating layer further comprises a dielectric pad layer formed upon the substrate, and the substrate further comprises single crystalline material beneath the window opening.